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data book 1 12.99 hys 64v4300gu sdram-modules 3.3 v 4m 64-bit 1 bank sdram module 168-pin unbuffered dimm modules the hys 64v4300 is an industry standard 168-pin 8-byte dual in-line memory module (dimm) which is organized as 4m 64 in an one bank high speed memory arrays designed with 64 mbit synchronous drams for non-parity applications. the dimms use -7.5 speed sorted 4m 16 sdram devices in tsop54 packages to meet the pc133-333 requirements and -8 parts for the standard pc100 applications. decoupling capacitors are mounted on the pc board. the pc board design is according to intels module specification. the dimms have a serial presence detect, implemented with a serial e2prom using the 2-pin i 2 c protocol. the first 128 bytes are utilized by the dimm manufacturer and the second 128 bytes are available to the end user. all infineon 168-pin dimms provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint., ? 168 pin unbuffered 8 byte dual-in-line sdram modules for pc main memory applications ? pc100 and pc133 versions ? one bank 4m 64 organization ? optimized for byte-write non-parity ? jedec standard synchronous drams (sdram) ? fully pc board layout compatible to intels latest module specification ? sdram performance: ? programmed latencies: ? single 3.3 v ( 0.3 v) power supply ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? decoupling capacitors mounted on substrate ? all inputs and outputs are lvttl compatible ? serial presence detect with e 2 prom ? utilizes 4m 16 sdrams in tsopii-54 packages with 4096 refresh cycles every 64 ms ? 133.35 mm 29.31 mm 4.00 mm card size with gold contact pads -7.5 -8 unit pc133 pc100 f ck clock frequency (max.) 133 100 mhz t ac clock access time 5.4 6 ns product speed cl t rcd t rp -7.5 pc133 3 3 3 -8 pc100 2 2 2
hys 64v4300gu sdram-modules data book 2 12.99 note: all part numbers end with a place code (not shown), designating the die revision. consult factory for current revision. example: HYS64V4300GU-8-b, indicating rev.b dies are used for sdram components. ordering information type code package description module height hys 64v4300gu-7.5- pc133-333-520 l-dim-168-32 133 mhz 4m 64 1 bank sdram module 1.15 hys 64v4300gu-8- pc100-222-620 l-dim-168-32 100 mhz 4m 64 1 bank sdram module 1.15 pin definitions and functions a0 - a11 address inputs (ra0 ~ ra11 / ca0 ~ ca7, ca10) clk0 - clk3 clock input ba0, ba1 bank select dqmb0 - dqmb7 data mask dq0 - dq63 data input/output cs0 - cs3 chip select cb0 - cb7 check bits (x72 organization only) v dd power (+ 3.3 v) ras row address strobe v ss ground cas column address strobe scl clock for presence detect we read/write input sda serial data out for pres. detect cke0, cke1 clock enable n.c./du no connection address format part number rows columns bank select refresh period interval 4m 64 hys 64v4300gu 12 8 2 4k 64 ms 15.6 m s
hys 64v4300gu sdram-modules data book 3 12.99 pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1 v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 du 86 dq32 128 cke0 3 dq1 45 cs2 87 dq33 129 cs3 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 v dd 48 du 90 v dd 132 n.c. 7dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 n.c. 92 dq37 134 n.c. 9 dq6 51 n.c. 93 dq38 135 n.c. 10 dq7 52 n.c. 94 dq39 136 cb6 11 dq8 53 n.c. 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 n.c. 103 dq46 145 n.c. 20 dq15 62 du 104 dq47 146 du 21 n.c. 63 cke1 105 n.c. 147 n.c. 22 n.c. 64 v ss 106 n.c. 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 n.c. 66 dq22 108 n.c. 150 dq54 25 n.c. 67 dq23 109 n.c. 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we 69 dq24 111 cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 cs0 72 dq27 114 cs1 156 dq59 31 du 73 v dd 115 ras 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 clk2 121 a9 163 clk3 38 a10 80 n.c. 122 ba0 164 n.c. 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 clk1 167 sa2 42 clk0 84 v dd 126 n.c. 168 v dd
hys 64v4300gu sdram-modules data book 4 12.99 functional block diagrams block diagram: 4m 64 one bank sdram dimm modules (hys 64v4300gu) spb04204 dq0-dq7 ldqm cs d0 cs0 dq0-dq7 dqmb0 dq0-dq7 dq32-dq39 dqmb4 ldqm d2 cs a0-a11, ba0, ba1 d0-d3, (d4) cc v ss v c ras, cas, we cke0 clk1, clk3 clock wiring 4 m x 64 clk0 2 sdram + 15 pf termination clk1 2 sdram + 15 pf clk2 clk3 47 k scl scl 2 sa0 sa1 sa2 e prom (256 word x 8 bit) sa1 sa0 sa2 sda wp w dqmb1 dq8-dq15 dqmb5 dq40-dq47 udqm dq8-dq15 udqm dq8-dq15 dq56-dq63 dq48-dq55 dqmb6 dqmb7 dqmb3 dq24-dq31 dqmb2 dq16-dq23 cs2 cs dq8-dq15 udqm ldqm dq0-dq7 d1 cs dq8-dq15 udqm ldqm dq0-dq7 d3 all resistors are 10 notes: 1) w dimm may combine bytes 0 with 4, 1 with 5, 2 with 6 and 3 with 7 to obtain 2) most advantagous board layout to obtain minimum dq trance length 10 pf d0-d3, (d4) d0-d3, (d4) d0-d3, (d4) d0-d3 termination
hys 64v4300gu sdram-modules data book 5 12.99 dc characteristics t a = 0 to 70 c; v ss = 0 v; v dd ; v ddq = 3.3 v 0.3 v parameter symbol limit values unit min. max. input high voltage v ih 2.0 v dd +0.3 v input low voltage v il C0.5 0.8 v output high voltage ( i out =C4.0ma) v oh 2.4 C v output low voltage ( i out =4.0ma) v ol C0.4v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) C10 10 m a output leakage current (dq is disabled, 0 v < v out < v dd ) i o(l) C10 10 m a capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit max. input capacitance (a0 - a11, ras , cas , we ) c i1 35 pf input capacitance (cs0 ,cs2 ) c i2 25 pf input capacitance (clk0 - clk3) c icl 35 pf input capacitance (cke0) c i3 30 pf input capacitance (dqmb0 - dqmb7) c i4 13 pf input /output capacitance (dq0 - dq63, cb0 - cb7) c io 10 pf input capacitance (scl, sa0-2) c sc 8pf input /output capacitance c sd 10 pf
hys 64v4300gu sdram-modules data book 6 12.99 operating currents 1 t a = 0 to 70 c, v dd = 3.3 v 0.3 v (recommended operating conditions unless otherwise noted) parameter test condition symbol -7.5 -8 unit note max. operating current t rc = t rc(min.) , t ck = t ck(min.) outputs open, burst length = 4, cl=3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access C i cc1 140 130 ma 1) precharge standby current in power down mode cs = v ih (min.) , cke v il(max.) t ck =min i cc2p 22ma 1) t ck =infinity i cc2ps 11ma 1) precharge stand-by current in non power down mode cs = v ih (min.) , cke 3 v ih(min.) t ck =min i cc2n 40 35 ma 1) t ck =infinity i cc2ns 55ma 1) no operating current t ck = min., cs = v ih (min.) , active state (max. 4 banks) cke 3 v ih(min.) i cc3n 50 45 ma 1) cke v il(max.) i cc3p 88ma 1) burst operating current t ck =min read command cycling C i cc4 110 100 ma 1, 2) auto refresh current t ck =min auto refresh command cycling C i cc5 140 130 ma 1) self refresh current self refresh mode cke = 0.2 v i cc6 11ma 1)
hys 64v4300gu sdram-modules data book 7 12.99 ac characteristics 3,4 t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max. clock and access time clock cycle time cas latency = 3 cas latency = 2 t ck 7.5 10 C C 10 10 C C ns ns C system frequency cas latency = 3 cas latency = 2 f ck C C 133 100 C C 100 100 mhz mhz C access time from clock cas latency = 3 cas latency = 2 t ac C C 5.4 6 C C 6 6 ns ns 4), 5) clock high pulse width t ch 2.5 C 3 C ns 6) clock low pulse width t cl 2.5 C 3 C ns 6) setup and hold parameters input setup time t cs 1.5 C 2 C ns 7) input hold time t ch 0.8 C 1 C ns 7) power down mode entry time t sb C1C1clk 8) power down mode exit setup time t pde 1C1Cclk 9) mode register setup time t rsc 2C2Cclk transition time t t 1C1CnsC common parameters ras to cas delay t rcd 20 C 20 C ns C precharge time t rp 20 C 20 C ns C active command period t ras 45 100k 50 100k ns C cycle time t rc 67.5 C 70 C ns C bank to bank delay time t rrd 15 C 16 C ns C cas to cas delay time (same bank) t ccd 1C1CclkC
hys 64v4300gu sdram-modules data book 8 12.99 notes 1. these parameters depend on the cycle rate. these values are measured at 133 mhz for -7.5 and at 100 mhz for -8 modules. input signals are changed once during t ck , excepts for i cc6 and for stand-by currents when t ck = infinity. all values are shown per memory component. 2. these parameters are measured with continuous data stream during read access and all dq toggling. cl = 3 and bl = 4 are assumed and the v ddq current is excluded. 3. all ac characteristics are shown for device level. an initial pause of 100 m s is required after power-up. then a precharge all banks command must be given followed by eight auto refresh (cbr) cycles before the mode register set operation can begin. 4. ac timing tests have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1 ns with the ac output load circuit shown in figure below. specified t ac and t oh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v/ ns edge rate between 0.8 v and 2.0 v. 5. if clock rising time is longer than 1 ns, a time ( t t /2 - 0.5) ns must be added to this parameter. 6. rated at 1.4 v. 7. if t t is longer than 1 ns, a time ( t t - 1) ns must be added to this parameter. refresh cycle refresh period (4096 cycles) t ref C64C64ms self refresh exit time t srex 1C1Cclk 10) read cycle data out hold time t oh 3C3Cns 4) data out to low impedance time t lz 0C0CnsC data out to high impedance time t hz 3738ns 11) dqm data out disable latency t dqz C2C2clkC write cycle data input to precharge (write recovery) t wr 2C2CclkC dqm write mask latency t dqw 0C0CclkC ac characteristics (contd) 3,4 t a = 0 to 70 c; v ss = 0 v; v dd = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit note -7.5 pc133-333 -8 pc100-222 min. max. min. max.
hys 64v4300gu sdram-modules data book 9 12.99 8. whenever the refresh period has been exceeded, a minimum of two auto (cbr) refresh commands must be given to wake-up the device. 9. timing is a asynchronous. if setup time is not met by rising edge of the clock then the cke signal is assumed latched on the next cycle. 10.self refresh exit is a synchronous operation and begins on the second positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to t rc is satisfied after the self refresh exit command is registered. 11.this is referenced to the time at which the output achieved the open circuit condition, not to output voltage levels. a serial presence detect storage device - e 2 prom - is assembled onto the module. information about the module configuration, speed, etc. is written into the e 2 prom device during module production using a serial presence detect protocol (i 2 c synchronous 2-wire bus). 50 pf i/o measurement conditions for t ac and t oh spt03404 clock 2.4 v 0.4 v input hold t setup t t t output 1.4 v t lz ac t t ac oh t hz t 1.4 v cl t ch t
hys 64v4300gu sdram-modules data book 10 12.99 spd-table byte# description spd entry value hex 4m 64 -7.5 4m 64 -8 0 number of spd bytes 128 80 80 1 total bytes in serial pd 256 08 08 2 memory type sdram 04 04 3 number of row addresses (without bs bits) 12 0c 0c 4 number of column addresses 8 08 08 5 number of dimm banks 1 01 01 6 module data width 64 40 40 7 module data width (contd) 0 00 00 8 module interface levels lvttl 01 01 9 sdram cycle time at cl = 3 7.5/10.0 ns 75 a0 10 sdram access time from clock at cl = 3 5.4/6.0 ns 54 60 11 dimm config (error det/corr.) none 00 00 12 refresh rate/type self-refresh, 15.6 m s80 80 13 sdram width, primary x16 10 10 14 error checking sdram data width n/a 00 00 15 minimum clock delay for back-to-back random column address t ccd =1 clk 01 01 16 burst length supported 1, 2, 4, 8 & full page 8f 8f 17 number of sdram banks 4 04 04 18 supported cas latencies cl = 2 & 3 06 06 19 cs latencies cs latency = 0 01 01 20 we latencies wl = 0 01 01 21 sdram dimm module attributes non buffered/non reg. 00 00 22 sdram device attributes: general v dd tol. 10% 0e 0e
hys 64v4300gu sdram-modules data book 11 12.99 byte# description spd entry value hex 4m 64 -7.5 4m 64 -8 23 minimum clock cycle time at cas latency = 2 10.0 ns a0 a0 24 maximum data access time from clock for cl = 2 6.0 ns 60 60 25 minimum clock cycle time at cl = 1 not supported ff ff 26 maximum data access time from clock at cl = 1 not supported ff ff 27 minimum row precharge time 20 ns 14 14 28 minimum row active to row active delay t rrd 15/16 ns 0f 10 29 minimum ras to cas delay t rcd 20 ns 14 14 30 minimum ras pulse width t ras 45 ns 2d 2d 31 module bank density (per bank) 32 mbyte 08 08 32 sdram input setup time 1.5/2 ns 15 20 33 sdram input hold time 0.8/1 ns 08 10 34 sdram data input setup time 1.5/2 ns 15 20 35 sdram data input hold time 0.8/1 ns 08 10 36-61 superset information (may be used in future) Cffff 62 spd revision revision 1.2 12 12 63 checksum for bytes 0 - 62 C C df 64-125 manufacturers information (optional) (ff h if not used) CCxx 126 max. frequency specification 64 64 127 details C af af 128+ unused storage locations C ff ff spd-table (contd)
hys 64v4300gu sdram-modules data book 12 12.99 package outlines gld09263 133.35 10 11 3 6.35 6.35 41 40 42.18 84 127.35 3 1.27 0.1 85 94 95 124 125 168 2 17.78 0.1 4 3 min. 4 max. 29.31 detail of contacts min. 2.54 1 0.05 1.27 1 1.27 91 x 1.27 = 115.57 3.125 0.2 0.15 66.68 l-dim-168-32 sdram dimm module package

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